Functional Specifications

• SPANKy uses an eight bit word, meaning all integer values and address are eight bits long. All integers are two's-complement values, allowing a range of -128 to 127. Addresses are unsigned.
• SPANKY is Big Endian, as all systems should be.
• SPANKy has 16 bit instructions. That allows three-address instructions, but requires a two-cycle instruction fetch stage.
• SPANKy has four bit opcodes. We use four bits to encode 16 instructions, which are described below.
• SPANKy has 16 architected general purpose registers. We do not assign any special meaning to any of these register, for symmetry (unlike our 32 bit competition, who often create special semantics for a few registers). Due to limited silicon space, our chip only implements eight of the 16 architected registers. Thus registers 8 through 15 are mapped to registers 0 through 7.
• SPANKy has separate instruction memory and data memory. Historically this approach has been termed the Harvard style, although SPANKy cannot condone the institution in general. Each memory has an eight bit address space, giving us 256 eight bit words each, or a total of 512 bytes of addressable memory. SPANKy's memory will reside in off-chip SRAM.
• SPANKy implements limited hardware memory protection. Instruction memory is read-only, and data memory cannot be executed.
• SPANKy completes all instructions in a four cycle loop: two cycles to fetch the instruction, one cycle to execute the instruction, and one cycle to write the result back to the register file. The writeback cycle overlaps with the first fetch of the next instruction, bringing SPANKy's throughput up to 1/3 IPC.
• SPANKy can pause and resume execution using HALT instructions and the RUN signal. This ability allows users to interact with SPANKy, reading and writing to the memory bus manually, and using the RUN signal to control the speed of the processor.
• SPANKy has a ripple-carry adder, a barrel-shifter, a logic unit realizing the AND, OR, and NOT operations, and a branch unit. To reduce the load on the main busses, transmission gates disable any functional unit that is not in immediate use.
• SPANKy does all computation between the clkb and clka signals. Accessing off-chip memory will be the critical path for SPANKy, and occurs during that portion of the clock cycle. Therefore placing all other computation in that same portion allows us to minimize the time between the clka and following clkb signals, reducing wasted time and maximizing the overall clock frequency. This decision also simplifies control, because the PLA outputs only VbSa signals, which must be modified for use during the other half of the clock cycle.
• SPANKy has 40 pins total:
  • 6 pins bring in Vdd and GND
  • 2 pins bring in clock signals
  • 1 pin is a reset signal
  • 1 pin is a run signal
  • 8 pins connect the data bus to the off-chip memory
  • 9 pins address the off-chip memory
  • 2 pins control the read/write signals for the memory
  • 2 pins send out state machine information, for testing purposes.
  • 8 pins send out the contents of the writeback bus, also for testing.
  • 1 pin is unused.
  View pin layout