SPANKy is for lovers
SPANKy!
Brought to you by group GAMMA:
Victoria Smith (vics@rice.edu)
Mara Prandi-Abrams (mabrams@rice.edu)
Dennis Geels (geels@rice.edu)
Overview -
Functional Specifications -
ISA -
Controller -
Design and Layout -
Performance Analysis -
Summary
423 Final Report
Description of Omnilab Equipment and Interconnection
We used the basic set-up for Omnilab. We originally tried to interface our
chip to an off-chip memory, buffered from the chip with 377 chips. This
did not work, so we just tested our chip and had the stimulus act as our
off-chip memory. By the time we got our chip working at all it became
obvious that our address bus was not working properly and would not be able
to interface with the memory. So our final set-up consisted of hooking up the stimulus pins to our chips and analyzing all of our pins from our chip to see if it functioned correctly.
Number and Types of Test Vectors Used
Our test vector started out with a complex shift-and-add multiply algorithm.
The idea was to load the program to off-chip memory and run it. When this
failed we used our test vector to simulate memory accesses. It became obvious
when this, too, failed, that the problem was more fundamental than this;
nothing, not even the state machine, was outputting anything at all. We then
struggled to get a simple vector which only asserted the RESET and RUN
signals.
Eventually we realized that off-chip memory was not going to work, and we
created a new set of test vectors. Each test manually loaded a few values
into the chip's registers, and then fed all combinations of those values to
one of the functional units. We ended up with separate test vectors for each
of the following: adder, OR unit, AND unit, inverter, barrel shifter, and
branch/halt.
Number of Chips that are Functional and Reasons for Disfunctional Chips
Well, we had some problems initially, and we ended up burning out four of
our five chips (either connecting power to ground or disconnecting power
from itself). We eventually discovered that our padframe was left upside-down
for the fabrication of the chip, and therefore we were connecting all of the
pins (including power and ground) backwards. By the time we found this error,
only one chip remained for real testing. Note that each of the five chips
showed proper power-to-ground resistance prior to testing.
The remaining chip was almost fully functional. The main problem was that the
two least significant bits of our address bus were pulled low most of the time
(it looks like a drive strength problem or a floating transmission gate
problem). Other than this our chip looked very functional, but without more
usable chips it is impossible to know if the problem was a design flaw or a
fabrication problem. The design simulated perfectly before submitting it to
MOSIS, but it is of course possible that a driving strength problem is
killing the bus.
Comparison of Results with irsim Results: Simulation vs. Fabricated
Chip
Aside from the fact that the irsim simulation worked completely and the
fabricated chip did not, the results were very similar. The simulation
was functional up to speeds of about 50 MHz, which the fabricated chip could
not match.
Omnilab test output:
MEM[0:7] shows the contents of the
writeback bus - inputs for each test are all possible permutations of
[00000000],[11111111],and [01010101].
and unit
or unit
inverter
barrel shifter
adder
branch unit, halt
Speed Response of Chip
None of our chips were completely functional. The one chip that was mostly
functional continued to operate so up to a speed of
6.8MHz
. At the next faster testable speed
(17MHz),
output signals did not switch properly, results were non-deterministic, and
some signals oscillated on some inputs. At
34MHz,
the outputs were just flat wrong.
Any Special Problems or Suggestions
Our main problem was the confusion over the orientation of our padframe. We
suggest that in future years, each team would be allowed and encouraged to
inspect the CIF file returned by MOSIS. We, for instance, could have
immediately realized that our pinouts were upsidedown.
We also suggest a more reliable PC and printer arrangement, faster
workstations in the lab, and ideally a replacement for Omnilab with a better
interface.
MOSIS Report
View MOSIS Report