SPANKy Design and Layout

SPANKy!

Brought to you by group GAMMA:
Victoria Smith (vics@rice.edu)
Mara Prandi-Abrams (mabrams@rice.edu)
Dennis Geels (geels@rice.edu)
Overview - Functional Specifications - ISA - Controller - Design and Layout - Performance Analysis - Summary

423 Final Report

Circuit Design and Layout

Design

Our main goals for the design were simplicity and functionality.

View block diagram (with signal timing information)
View SPANKy plot

Layout

View floorplan (with pin information)
View cell hierarchy diagram

Subcells

branch unit GIF IRSIM output
3-to-8 decoder GIF IRSIM output
controller GIF IRSIM output
register 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
master-slave latch 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
clearable master-slave latch 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
2-to-1 mux 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
T-gate 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
adder 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
incrementor 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
logic unit 1bit GIF 1bit IRSIM output 8bit GIF 8bit IRSIM output
pc floorplan GIF layout GIF IRSIM output
barrel shifter floorplan GIF layout GIF IRSIM output

Verification

We tested SPANKy with a multiplication program, which produces a 16bit product of two 8bit numbers. Memory was emulated by directly controlling the data pins. The entire program took approximately 90 clock cycles to complete, making the IRSIM output difficult to read (although correct). Below is a copy of the last few cycles of the computation, as well as the full results of a smaller, 2bit multiplication.

View end of IRSIM test output
View IRSIM test output of shorter computation