SPANKy Control
SPANKy!
Brought to you by group GAMMA:
Victoria Smith (vics@rice.edu)
Mara Prandi-Abrams (mabrams@rice.edu)
Dennis Geels (geels@rice.edu)
Overview -
Functional Specifications -
ISA -
Controller -
Design and Layout -
Performance Analysis -
Summary
Controller PLA
- The RESTART signal sends SPANKy into an idle state.
- The RUN signal begins a three-state fetch, execute, writeback loop
- In phase 1, SPANKy fetches the first byte of an instruction, and
increments the PC.
- In phase 2, SPANKy fetches the next byte, while the opcode from the
first byte filters through the controller.
- In phase 3, SPANKy activates the appropriate functional unit, and
either increments the PC or lets the branch unit write a branch target
address to the PC.
- In phase 4, SPANKy writes any result to the register file, while
beginning phase 1 of the next instruction.
- A halt instruction sends SPANKy back into the idle state.
View state machine diagram
View MEG input file
View MEG summary file
View IRSIM command file
View IRSIM test output