Date | Topic | Discussion Leader |
---|---|---|
1/9 | Technology Overview | Rixner |
1/11 | No class | --- |
1/16 | Microarchitecture Overview | Rixner |
1/18 | Front End 1 | Rixner |
1/23 | Front End 2 | Rixner |
1/25 | Instruction-level Parallelism | Rixner |
1/30 | Superscalar Processing | Mike Foss and Anna Youssefi |
2/1 | VLIW | Angela Yun Zhu |
2/6 | Compilers | Yanjun Sun |
2/8 | Caching | Mihir Choudhury |
2/13 | No Class | --- |
2/15 | Data Prefetching | Adedotun Falade and Bryan Smith |
2/20 | Address Translation | Rob Smith and Angela Yun Zhu |
2/22 | DRAM | Rixner |
2/27 | Memory Bandwidth and Parallelism | Mike Foss |
3/1 | Project Proposals | Group Representatives |
3/6 | Vacation | --- |
3/8 | Vacation | --- |
3/13 | Clustered Architectures | Anna Youssefi |
3/15 | Simultaneous Multithreading | Mihir Choudhury and Yanjun Sun |
3/20 | Chip Multiprocessing | Rixner |
3/22 | Technology | Bryan Smith |
3/27 | Project Checkpoint | Group Representatives |
3/29 | Power Simulation and Modeling | Adedotun Falade |
4/3 | Low Power | Rob Smith |
4/5 | Vacation | --- |
4/10 | Modern Processors 1 | Rixner |
4/12 | Modern Processors 2 | Rixner |
4/17 | Project Presentations | Group Representatives |
4/19 | Project Presentations | Group Representatives |
4/24 | Course Wrapup | Rixner |
Scott Rixner, mailto:rixner@rice.edu