VLSI Design II class at Rice University - Spring 2004

• VLSI Design Faculty:
  • Joe Cavallaro

Fall 2003 - Spring 2004 - Project Groups

• Fall 2003 - Spring 2004 -  Project Groups Page
• Fall 2003 Chip Photos **NEW**

Handouts

Week 4

• D Algorithm for test generation from Weste
  Week 5
  
• Test Access Port overview and TI Data Sheet
  Week 6
  
• NAND demo Device Under Test Breadboard
• Omnilab Tutorial
• Sim2olab Conversion Utility Tutorial
• Omnilab Connector Diagrams
  Week 7
• Tektronix TLA-714 Logic Analyzer Programming
  Week 11
  
• Initial Padframe Testing Procedures
• 2002 Update to International Technical Roadmap for Semiconductors
  Week 12
  
• Notes on PGA84 Test Fixture
  Week 13
  
• Final Presentation Format Guide for April 21 Presentations
• Final Report Format Guide
• MOSIS Report Text Template File
  

Homework Assignments

Four homework and lab assignments on Test Vector Creation, Test Access Port, Lab Use of Logic Analyzers, and VLSI Design Cost Tradeoff Analysis.
• Homework #1 - Test Vector Creation and "D" Algorithm
• Homework #2 - Test Access Port and Scan Registers
• Homework #3 - Testing of 3-line to 8-line Decoder

  ---

  MOSIS Run Status

  The fall 2003 projects were fabricated using the AMI 0.5 micron CMOS process through MOSIS generously supported by the Semiconductor Industry Association.

  Course Contents

  The topics covered in this course include:
  • VLSI testing and test generation, including Test Access Port (TAP).
  • Creation of a basic standard cell library from layout leafcells.
  • Software for automatic test generation.
  • Use of FPGAs for design verification.
  • Manufacturability and manufacturing yield analysis.
  • Economics and cost factors in VLSI ASIC design and manufacturing.
  • Chip inspection using optical microscopy.

  Test Equipment

  The functional testing will be performed using specially equipped computers. Orion Omnilab test stations are attached to three PC's in the VLSI Design Center, Abercrombie Labs AL A116/A117. These PC's are networked and the test vector files prepared for Irsim can be converted to Omnilab format. A breadboard and connectors will be issued to the students. High speed testing can also be done with Omnilab up to about 17 MHz.

  A Tektronix Logic Analyzer with high speed stimulus is also available.

   

  ---

  About the Elec 422, VLSI Design I, class in Fall 2003 (last term).

  ---

  Joe Cavallaro
  Last modified: 21 April 2004