Elec 422: VLSI Design I
Fall 2003
Due: December 5, 2003
The final report is a group
report and will represent about half of your grade. Please be thorough in your
presentation. Your report should contain the following sections and will be
weighted accordingly. It is very important that you indicate in the closing
section, the “division of work” by the group members. All members of the group
must agree to this statement so that I have an accurate assessment of each
member’s contribution. It is required that the ”statement of work” page be
printed on paper, signed by each group member, and turned in to me. I am sorry
for the need for formality.
You should do your final report in electronic format
through updates and additions to your Elec422 course project Web page. Please
keep all html and graphics files in one directory and make all Web links
relative to the current page, so that the report can be easily archived to the
Elec422 Web Page during summer 2004. The course project Web page should be
reasonably complete and give a thorough overview of the design. Please create a
“tar” or “zip” archive of the files and e-mail me the location when the report
is completed.
1.
Functional Description (10 points):
Pin-map Showing Signal Name and Physical Pin Number:
Functional Test Strategy and Output Test Signals:
2.
Circuit Design (25 points):
Logic Diagrams:
System Timing Diagram:
Irsim
Results of Subcells:
Irsim
Results of Entire Chip:
3. PLA Description (10 points):
Input to meg:
Irsim
Simulation:
4.
Circuit Layout (30 points):
Plots of low-level Cells (using cif2ps
or pplot):
Cell Hierarchy:
Floor plan:
Full plot of Chip (using X window dump or xv or PC Xwin32 screen
capture):
5.
Performance Analysis; Maximum clock frequency (15 points):
Crystal Analysis of longest path (5 points):
Spice
Analysis of critical sub-circuit (10 points):
6.
Summary
References
Division of Work by Group Members
Comments and Suggestions on CAD tools
Note:
Format and style (10 points)