Elec 422, VLSI Design I

Fall 2003

Class Presentation Guidelines

AMD Design Contest Presentations

 

Presentations: DH1049, Thursday December 4, 2003, 2:30-5:30pm

 

Presentation Format

Each group will have about 15 minutes to make their presentation to the class. The group should prepare an electronic presentation with PowerPoint that describes the project. Please make sure that the fonts are large enough to be readable in the classroom / conference room. To show sections of the layout, please use cif2ps, pplot, xv, xwd, or Xwin32 PC captured plots as part of the presentation. I will have a laptop and projector available. There is no PC in DH1049 this year, but you can bring your own laptop. I would like to archive these on the class web site, so in any case, please e-mail me your presentation in advance.

 

Project Summary Statement

Please e-mail to me a required one page summary statement of your project and its status by noon on Tuesday, December 2, 2003. I will collect all statements and e-mail to the class and the AMD judges on that Tuesday night. This will help the judges prepare questions. Each project group will have one “vote” during the contest and will rank the top 3 best projects.

 

Organization of Presentation

Each member of the group should discuss the section that is their respective specialty, and plan on a brief 3-minute overview per person. Due to the limited amount of time, you should present the key, unique features of your design. The following topics should be presented:

 

1. Functional Description of Chip and Project Completion Status

How much is completed; what needs to be done

 

2. Circuit Design

Logic Diagrams

System Timing Diagrams – how two phase clocking is distributed to blocks

 

3. PLA Description

State Transition Diagram – how control flow proceeds in your design

Input to meg, brief summary

 

4. Layout

Plots of selected low-level Cells

Cell Hierarchy

Floor plan

Full plot of Chip

 

5. System Performance Analysis

Crystal Analysis of Longest Path

Spice Analysis of Critical Sub-Circuit, and predicted clock frequency

 

6. Testability Analysis

Functional Test Strategy – Spring testing requirements – external RAM, I/O, etc.

Output Signals for Testability (State Bits, etc.)