|
| slat.cmd.txt
|
| Comments
| Elec422 HW1 Problem 3
| CMOS Static Latch
| Fall 2003
| Please submit the output generated by irsim for this command file
| clock definition of Vdd as constant 1 allows irsim to read
| the "V" input commands without a real clock signal in this problem
| Please MARK UP the irsim output with color hightlights to
| to explain in words what is happening with each store sequence
| in terms of data_in values captured.
| 
logfile slat.log
ana store data_in data_out
w   store data_in data_out
V store   1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0
V data_in 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0
clock Vdd 1
R