Elec 422: VLSI Design I

Homework 1

Fall 2003, September 11, 2003

Independent work is expected.

Due: 4pm, Friday, September 26, 2003.

For each of the following problems:

(a) Draw a logic diagram using Inverter, NAND, NOR, Transmission gate, etc. symbols,

(b) Draw a transistor-level circuit diagram indicating the NMOS and PMOS transistors,

(d) Use magic_05 to draw the layout for the MOSIS AMI 0.5 micron process. Create a CIF file and use cif2ps or pplot to plot the layout.

(e) Create the circuit extractor files within magic_05. Complete the extraction of the circuit using ext2sim -R -t ! for use with the irsim simulator,

(f) Perform an exhaustive irsim simulation, (as described below), testing all possible combinations of input and control signals. Please submit the irsim test vector files along with the graphical output of the irsim simulation. Use irsim scmos30.prm file.sim to invoke the scalable CMOS parameter file for the 0.5 micron MOSIS process.

Notes:

Assume that only the original signals are available. Any complement of a signal must be generated within the circuit with an inverter.
All nodes within the circuit must be clearly labeled. Use point labels instead of box or line labels to label nodes in magic_05. Always label power as Vdd! and ground as GND! . Careful labels in the top-level cell is key to accurate simulation. You can view the output of ext2sim with a text editor like emacs or vi to see if your circuit nodes are in the .sim file. Many simulation problems come from inadvertent aliases or incorrect labels.
Use compound gates, that is, and-or-invert structures where possible.
Use static complementary logic only.
Be sure to include sufficient substrate contacts in your stick diagram and magic layout.
Hand in all of the above items (a) through (f) and also send an e-mail to cavallar@rice.edu, gadhiok@rice.edu, and rpredrag@rice.edu indicating the location of your magic and irsim files to help with grading. Please do this within 24 hours of handing in your solutions.

Problem 1. Basic Logic Gate Design

Design a 2-input NAND and a 2-input NOR gate using magic. Use a style where Vdd and GND run horizontally in metal1, with input signals on the left and output signals on the right. Choose the same separation between Vdd and GND for both cells, approximately 50 to 60 lambda units. Use irsim to simulate each of these logic gates, and test all cases.

Problem 2. Logic Expressions

Perform the above operations for the following logical expression:

Be sure to test all 64 possible input signal patterns with irsim. (See the discussion in Weste, 2ed, pp. 15-17.)

Problem 3. Static Latch

Design a one-bit level-sensitive static latch. Label the input data as data_in, the control signal as store, and storebar, and the output as data_out. Use magic cell hierarchy to design the latch. In order to simplify the layout, use an inverter cell as a subcell in this problem. The top-level parent cell, latch, will contain two children cells, inverter_0 and inverter_1. When using cell hierarchy in magic, make sure that the labels, data_in, data_out, store, and storebar, are placed on a square of paint contained in the top-level parent cell, latch.

Generate storebar from store by using a separate inverter. Place this inverter below the latch cell so that it can provide the storebar signal for the multi-bit latch in the next problem.

When testing the latch, the data and control signals should not both be changing at the same time. The data should remain stable or valid as the latch control signal goes low. Test the ability of the latch to store both “0” and “1”. (See the discussion in Weste, 2ed, pp. 19-21.) (First use your own irsim command file. Then use the irsim command file on the class web site, slat.cmd.txt, and save as slat.cmd for second irsim simulation.)

Problem 4. Barrel Shifter

Design a 4-bit barrel shifter. Connect the output result lines to a 4-bit static latch. Use the latch cell designed in the above problem. A single inverter can be used to produce storebar from store to control the 4-bit latch. Although this is a complex circuit, please draw complete total logic, transistor, and stick diagrams for all portions of the circuit!!! It can be big and ugly, but it is useful in this first homework to get total system topology and view. In the irsim simulation, test the effectiveness of the latch to store data, and to provide isolation from changing data in the barrel shifter.

Note: Assume that only one of the barrel shifter control signals can be active at a given time. You do not need to enforce this in hardware; it is sufficient to enforce this condition in the test vector file. However, do provide an inverter to generate each of the shiftbar signals.

Also, you do not need to test all possible barrel shifter data combinations. However, a 4-bit barrel shifter will have a 7-bit input word. You should test all possible shifts (four cases), and the ability of the latch to store both a “0” and a “1” for each possible shift. (See the discussion in Weste, 2ed, pp. 560-563.) (First use your own irsim command file for simuation. Then use irsim command file on the class web site, barrel.cmd.txt and save as barrel.cmd for your second irsim simulation.)