|
| barrel.cmd.txt
|
| Comment lines start with |
|
| Elec 422 HW1 Problem 4
| CMOS 4x4 Transmission Gate Barrel Shifter with Static Latch Array
| Fall 2003
| Please submit the output generated by irsim for this command file
| input data literals are l6, l5, l4, l3, l2, l1, l0
| l6 is MSB, l0 is LSB in terms of input data bits
| barrel shifter control is shift3, shift2, shift1, shift0
| outputs of barrel shifter before latches are sr3, sr2, sr1, sr0
| latch control (or enable) signal for all 4 latches is store
| final outputs of latch are result3, result2, result1, result0
| clock definition of Vdd as constant 1 allows irsim to read
| the "V" input commands without a real clock signal in this problem
| Please MARK UP the irsim output with color hightlights to
| to explain in words what is happening with each shift and store
| sequence in terms of data values (literals 0 through 6) captured.
| Note that not all shifted sequences are actually stored.
| Also explain what happens when all shift lines are low "0" and
| we try to latch a value; or when multiple shift lines are high "1".
|
logfile barrel.log
ana l6 l5 l4 l3 l2 l1 l0 shift3 shift2 shift1 shift0 sr3 sr2 sr1 sr0
ana store result3 result2 result1 result0
w   l6 l5 l4 l3 l2 l1 l0 shift3 shift2 shift1 shift0 sr3 sr2 sr1 sr0
w   store result3 result2 result1 result0
| First data set
V l6      1
V l5      1
V l4      0
V l3      1
V l2      0
V l1      0
V l0      1
V shift3  1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V shift2  0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
V shift1  0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0
V shift0  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
V store   1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0
clock Vdd 1
R

| Second data set
V l6      1
V l5      1
V l4      0
V l3      0
V l2      1
V l1      1
V l0      0
V shift3  1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
V shift2  0 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0
V shift1  0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0
V shift0  0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0
V store   1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0

clock Vdd 1
R