1 MOSIS pad frame

Please do not modify the I/O pads. The 0.5 micron AMI pads are on Owlnet in locations specified in the Padframe Notes on the class web page.)

Make sure that you do a final irsim simulation of the chip after you have connected the pads to your design. (It is important to test from the padframe since internal shorts in your design may become apparent when the padframe inverters drive the core of your circuit, instead of irsim vectors forcing inputs into your chip core.) Paint some metal1 over the metal1 connection between the bonding section of the pad and the pad internal circuitry in the top level cell, and label appropriately. You make wish to call a signal “data1” internally and “p_data1” at the I/O pad. Don’t forget that there are special Vdd and GND pads to provide power to the internals of the chip. Once you have included the PadFrame.mag padframe in your design and completed the wire routing, you will need to create a final CIF file.

2 Final CIF File

Please read Magic Tutorial 9: Format Conversion for CIF and Calma in the Elec 422 manual.

Note: Reading and writing CIF can take about 10 minutes or so at this stage. From within magic:

:cif ostyle lambda=0.30(c)

:cif write project

:quit

Now create a new directory, copy the CIF file there, and read it back into magic to make sure that there are no final Design Rule Errors due to the creation of the well region. It is important to make a subdirectory since a CIF file is an archive containing all your magic files and CIF reading needs an empty directory to not clobber your existing magic cells. The errors typically are due to spacings between P channel transistors especially in neighboring cells. At the final CIF stage you can paint nwell (:pai nwell) to close the gap in subcells and then delete the error causing fragments in the next level up parent cell. Problems can also occur due to diffusion contact to substrate contact spacing when alternate mirroring is used. It is best to leave a 4 lambda unit space from diffusion contacts to substrate contacts along a Vdd or GND line.

mkdir finalchip

cp project.cif finalchip

cd finalchip

magic

:cif istyle lambda=0.30(c)

:cif read project

Check for Design Rule Errors, and correct if necessary.

:writeall

:quit

You will now have the final magic files with corrections. Start Magic again and create a final CIF file if corrections were made.

:cif ostyle lambda=0.30(c)

:cif write submit

:quit

3 CIFflat file creation

The current version of magic contains an alternative method to create a “flattened” CIF file, which should lessen the problems with design rule errors due to nwell. I do not recommend the CIFflat file creation since you loose all design hierarchy. Start magic again and create a flattened CIF file as follows:

:cif ostyle lambda=0.30(c)

:cif flat submit

:quit

There are, however, three limitations to this process:

LARGE amounts of memory are used. The Sun’s may run out of memory. You may need to run on a lightly loaded machine or on one of the “compute” server machines, such as jungle.
A very LARGE CIF file is created, usually 1 to 2 MB. This may cause problems with your disk quota.
All labels will be lost in the flattening process and you will be left with only one magic cell. You will need to relabel the pads and then run irsim to validate the final layout.

4 Minimum Density Rules.

Be careful about the MOSIS minimum density rules which 15% for poly and 30% for the metal1 and metal2 layers. We have creating some basic Perl Scripts to check for poly and metal density. They are similar to the MOSIS software but work on magic files instead of CIF files and have some roundoff errors. The require an additional “flattened” magic database of your design. Please use these scripts contained in /home/cavallar/bin. There are three currently: one for metal1 in small frame called calc_metal1.pl and two for

poly, small frame calc_poly.pl and large frame calc_poly_double.pl

Be careful about any logos that produce design rule errors. These must be fixed so that the material is a valid shape.