Elec 422: VLSI Design I
Fall 2002
Final MOSIS Project Checklist.
DUE: TUESDAY, DECEMBER 10, 2002 by 5 pm
Please
refer to the companion Final Notes document for more details. Please complete
this checklist, print it out, and attach your “Division of Work” statement,
sign by all group members and return to me by 5 pm Tuesday December 10, 2002.
q
MOSIS Project Description
q
Final CIF File
and Location
q
Project
PowerPoint Presentation from AMD contest for archiving
q Web Page status. Please send e-mail when complete
q Additional Materials – I/O Pin list
q
Final Irsim –
Test vector files and Postscript Results
Final Project Checks- Important Items to verify:
q Verify Vdd and GND connectivity
q Make sure that the Vdd strap in the PLA is connected.
q Extractor warnings and warnings from ext2sim resolved for Vdd, GND, clka, clkb. Please justify any unresolved warnings here.
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q Please verify that the PLA description does
not contain any same state loops
q Please
verify that there are no Design Rule Errors and that all well and substrate
contact issues have been fixed.
q
Be careful about substrate contacts of the wrong
polarity.
q
Be careful about the MOSIS minimum density rules which
15% for poly and 30% for metal layers.
q Please fix about any logos that produce design rule errors.
Please Attach “Division of Work” Statement here.