Rice University

Elec 422, VLSI Design I

Course Information, Fall 2002

1 Organization

Day & Time: TTh 2:30-3:50pm, Location: Duncan Hall 1070

Web Page: http://www.owlnet.rice.edu/~elec422/

Instructor: Joe Cavallaro, DH 3042, x4719, cavallar@rice.edu

Lab Assistants: TBA, probably Marjan Karkooti

2 Topics

Logic Design and Simulation.

“Stick” Diagrams. Hierarchical Layout Methodology.

Mask Level Computer-Aided Design Tools: irsim, magic, spice...

Higher Level Design tools including Cadence and Xilinx prototyping.

State Machine Design and Programmable Logic Arrays.

System Routing, Clock Distribution, and I/O.

Design for Testability; Fault Tolerance. CMOS Processing.

MOSIS Scalable CMOS Design; 0.5 micron nwell process.

3 Required Textbooks

Weste & Eshraghian “Principles of CMOS VLSI Design” Second Edition, Addison-Wesley, 1993.

Also, notes and tutorials on the web site.

4 Course Requirements

** Students are required to enroll in Elec 423 VLSI Design II during Spring 2003. This is due to contractual obligations with the MOSIS Fabrication Service to provide a report on the success of the fabricated chip.

Group Project (Groups of four) to be fabricated by MOSIS.

Five Homeworks during first half of semester. (25%)

(Independent work under the Honor System is expected).

Midterm Exam (Take-home, Honor System, closed book, mid-November) (25%).

Project Presentation & Design Review (Last week of class, Thursday, Dec. 5) (10%).

Final Group Project Report (Due Friday Dec. 6) (40%).