|
Date
|
Week
|
Milestone
|
|
|
|
|
|
Aug. 29
|
1
|
Group Formation
|
|
Sept.3
|
2
|
Initial Project Idea – One Page Text and Block
Diagram
|
|
Sept. 3 - 6
|
2
|
Project Discussion during Office Hours
|
|
Sept. 10
|
3
|
One to Two Page Functional Description and Start
of WWW page
|
|
Sept. 10 - 13
|
3
|
Project Discussion during Office Hours
|
|
Sept. 17
|
4
|
Initial Logic and Algorithm Flow Due
|
|
Sept. 17 - 20
|
4
|
Project Discussion during Office Hours
|
|
Sept. 24
|
5
|
PLA Finite State Machine, Control and Timing
Description Due
|
|
Sept. 24 - 27
|
5
|
Project Discussion during Office Hours
|
|
Oct. 1
|
6
|
Initial Circuit Sub-Cell Layout Due
|
|
Oct. 1 - 4
|
6
|
Project Discussion during Office Hours
|
|
Oct. 8
|
7
|
Mid-Semester Project Status Report Due
|
|
Oct. 8 - 11
|
7
|
Mid-Semester Project Discussion during Office
Hours
|
|
Oct. 22
|
9
|
Datapath Circuit Module
Layout Due
|
|
Oct. 22 - 25
|
9
|
Project Discussion
during Office Hours
|
|
Oct. 29
|
10
|
System Integration, Floorplan, I/O Pads Placement
Due
|
|
Nov. 7
|
11
|
Mid-Term Exam, Take-home
|
|
Nov. 12
|
12
|
System Routing, System Simulation and Verification
Plan Due
|
|
Nov. 12 - 15
|
12
|
Project Discussion during Office Hours
|
|
Nov. 19
|
13
|
Final Electrical Rules Checks and Preliminary CIF
Due
|
|
Nov. 19 - 22
|
13
|
Final Design Evaluation of Layout during Office
Hours
|
|
Dec. 5
|
15
|
Project Presentation to Class
|
|
Dec. 5
|
15
|
Final Layout CIF file, Project Report, and WWW
Page Due
|
|
Dec. 9
|
|
Final Layout CIF file Due at MOSIS 0.5 micron
Process
|