From Eric Furbish:

Gotchas when simulating/ciffing tanner-ported 0.5u pads:

1.  There is a label called "hack" on both sides of some
    metal lines in the center of the pad.  Do not remove
    this label; it's there because the simulators don't
    understand that resistor layer that connects the two.
    If you remove it, irsim/spice/etc won't simulate the
    pads correctly.

2.  When you want to label your pads in the top-level
    layout, don't just paste "pad" layer over the pads
    and label it.  There is a cif output problem that
    makes pad layers at different levels of the hierarchy
    merge incorrectly.  This may cause MOSIS to reject
    your cif upon submission.  Instead, paste some M1
    over the section of M1 that runs under the pad but
    above the transistors at the bottom of the pad.  If
    you label this, and then forget to remove the label
    later, you still won't have cif submission problems.