Welcome to the VLSI Design I class at Rice University - Fall 2000
Electrical and Computer Engineering
422 at
Rice University
is designed to impart to the students the
theory and application
of VLSI design. The course includes a design project,
where students design original circuits based on the material learned
in class. The chips will be fabricated by
MOSIS ,
and tested in the next
class in this series, Elec 423 (VLSI II).
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VLSI Design Faculty:
-
Joe Cavallaro
Office Hours: T 4-5, W 3-4, Th 4-5, Duncan Hall 3042.
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Lab Assistants and Graders:
Newsgroup:
AMD Contest Presentations and Winners - Spring 2001
AMD Contest Presentations and Winners - Fall 2000
Fall 2000 - Project Groups
Fall 2000 - Administrative
Fall 2000 Handouts - Design Tools and Examples
Week 3
- UPDATED Notes on Running Magic and Irsim at Rice - 9/25/00
- Notes on Color Code for Stick Diagrams and Layout
- Notes on Inverter and Buffer Design, Layout and Simulation
- Notes on Substrate Contacts and Layout
Week 5
- Notes on PLA Design,
- - Text file containing "count.meg" PLA example,
- Notes on IRSIM Test Vectors,
- "A Clocking Discipline for Two-Phase Digital Systems," by D. Noice, R. Mathews, J. Newkirk,
Week 6
-
"A Formal Model of MOS Clocking Discplines," by K. Karplus,
Week 7
-
"Exclusion Constraints, a new application of Graph Algorithms to VLSI Design,"
by K. Karplus,
Week 8
- Notes on Crystal Timing Analysis
Week 9
- Notes on Spice Analysis of Pseudo-nmos
and Static Complementary CMOS Circuits
Week 10
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Notes on Spice Analysis of Dynamic Domino CMOS AND Gate Circuits
Week 11
Week 12
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HSPICE Simulation from Magic Layout
Week 13
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Guidelines on Final Class Presentation
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Guidelines on Final Project Report Format
Week 14
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Notes on Final Layout and Project Submission to MOSIS
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MOSIS notes on Padframe
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Padframe Numbering for External 40-pin MOSIS DIP Package
Week 15
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Class Presentation Schedule
Fall 2000 - Homework Assignments
Typically five homeworks during the first 10 weeks of the
semester covering these topics: Basic VLSI cell layout, Compound Gates,
Static Latch Design, Finite State Machine Design and PLA Implementation,
PLA Interfacing to Logic, System Timing Analysis, Other CMOS Logic Families,
Approximate RC Timing Analysis, Spice Circuit Analysis.
MOSIS Run Status
The fall 2000 projects are to fabricated using the
AMI 1.5 micron CMOS process through MOSIS
generously supported
by the
Semiconductor Industry Association.
The class projects are to be included in the December 2000 MOSIS run.
Course Topics
The topics covered in this course include:
- Overview of combinational Logic and minimization
- Sequential logic and Finite State Machines
- Overview of semiconductor physics
- PMOS and NMOS transistors
- CMOS fabrication technology (crystal growth, wafers, lithography, masks, doping, etc.)
- Layout, design rules, stick diagrams
- The latch-up effect, prevention, well contacts
- Common structures (gates, compound gates, latches, shifters, PLA's)
- Clocking strategies, 2-phase non-overlapping clock, Karplus methodology
- Design Process - hierarchical design (regularity, modularity, locality)
- Design verification tools (simulators, netlist comparators, DRC checkers, etc.)
- MOS equations, second-order effects.
- Biasing, AC and DC characteristics, load lines
- Circuit parameters, parameter extraction
- Timing, power, and size tradeoffs
- Other CMOS structures: dynamic CMOS, pseudo NMOS, BiCMOS
- Introduction to testing and testability
- Analog CMOS
Sections of Course Manual - Not Complete
CAD Tool Man pages
- Section 1 -
cif2ps, cifplot,
crystal, eqntott,
esim, ext2sim,
ext2spice, extcheck,
fsleeper, irsim,
magic, magicusage,
meg, mkcp,
mpla, net2ir,
nutmeg, pplot,
prepspice, rsleeper,
sconvert, sim2spice,
sleeper, spcpp,
spice.
- Section 3 -
irsim-analyzer,
mpack.
- Section 5 -
cmap,
displays,
dlys,
dstyle,
espresso,
ext,
glyphs,
magic,
mfbcap,
mpanda,
mpla,
net,
netchange,
sim,
simfile.
User contributed notes
Previous Years
About the VLSI Design class in
Fall 1999 (last year), and
Fall 1998, and
Fall 1997, and
Fall 1996, and
Fall 1995
Joe Cavallaro
Last modified: 09 August 2001