Welcome to the VLSI Design I class at Rice University - Fall 1998
Elec 422 at Rice is designed to impart to the students the
theory and application
of VLSI design. The course includes a design project,
where students design original circuits based on the material learned
in class. The chips will be fabricated by
MOSIS ,
and tested in the next
class in this series, Elec 423 (VLSI II).
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VLSI Design Faculty:
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Joe Cavallaro
Office Hours: T 4-5, W 3-4, Th 4-5, Duncan Hall 3042.
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Lab Assistants and Graders:
Fall 1998 Handouts - Administrative
Fall 1998 Handouts - Design Tools and Examples
Fall 1998 - Project Groups
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A - Douglas Laing, Juan Carlos Martinez, Walter Caro -
RISC Microprocessor
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B - John Cloudman, Melanie Demo, Ben Serebrin -
ALU with Stack and Division
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C - Kevin Rennie, V. Ajay Singh, Erik Sparrman -
ALU with Multiplication
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D - Steve Jahnke, Ruben Perez -
Serial Peripheral Interface
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E - Brad Buchanan, Ahsan Javed, Steve Tseng -
Vending Machine Controller
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F - Indra Neel Datta, Abhinav Dubey, Todd Waterman -
ALU with Square Root
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G - Tommy Hoang, Chen-Wei Pan, Khoa To -
Trigonometric Calculator
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H - Praful Kaul, Sridhar Rajagopal, Gang Xu -
Differencing Multistage Detector
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I - Daniel Liu, James Nicholson, Michael Simon -
ALU with Division
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J - Dennis Geels, Mara Prandi-Abrams, Victoria Smith -
"SPANKy" RISC Microprocessor
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K - Robert Glazewski, Paul Thomas -
ALU with Division
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L - Roger Borchers, Eston Ferguson, Howard Hicks -
ALU with Multiplication
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M - Anita Anderson, Neal Jameson, Michael Wakin -
Mini-CPU
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N - Christine Calkins, Britton Gregory -
RISC Microprocessor - CAGE
MOSIS Run Status
The fall 1998 projects are to fabricated using the
AMI 1.2 micron CMOS process through MOSIS. The class
projects are to be included in the December 1998 MOSIS run.
Course Topics
The topics covered in this course include:
- Overview of combinational Logic and minimization
- Sequential logic and Finite State Machines
- Overview of semiconductor physics
- PMOS and NMOS transistors
- CMOS fabrication technology (crystal growth, wafers, lithography, masks, doping, etc.)
- Layout, design rules, stick diagrams
- The latch-up effect, prevention, well contacts
- Common structures (gates, compound gates, latches, shifters, PLA's)
- Clocking strategies, 2-phase non-overlapping clock, Karplus methodology
- Design Process - hierarchical design (regularity, modularity, locality)
- Design verification tools (simulators, netlist comparators, DRC checkers, etc.)
- MOS equations, second-order effects.
- Biasing, AC and DC characteristics, load lines
- Circuit parameters, parameter extraction
- Timing, power, and size tradeoffs
- Other CMOS structures: dynamic CMOS, pseudo NMOS, BiCMOS
- Introduction to testing and testability
- Analog CMOS
Sections of Course Manual - Not Complete
User contributed notes
Previous Years
About the VLSI Design class in
Fall 1997 (last year), and
Fall 1996, and
Fall 1995
Joe Cavallaro
Last modified: 8 August 1999