Welcome to the VLSI Design I class at Rice University - Fall 2003
Electrical and Computer Engineering 422
at Rice University is designed to
impart to the students the theory and application of VLSI design. The
course includes a design project, where students design original
circuits based on the material learned in class. The chips will be
fabricated by MOSIS , and tested in
the next class in this series, Elec 423 (VLSI II).
- Lectures: TTH 2:30 - 3:50 Duncan Hall 1075
- VLSI Design Faculty:
- Lab Assistants and Graders:
Newsgroup:
Fall 2003 - Project Groups
Fall 2003 - Administrative
Fall 2003 Handouts - Design Tools and Examples
Week 1
-
Notes on Running Magic and Irsim at Rice
-
Notes on Color Code for Stick Diagrams and Layout
Week 2
- Notes on How to Create a Web Page at Rice Useful for VLSI Group Page Creation
-
Notes on Inverter and Buffer Design, Layout and Simulation
Week 3
-
Notes on Substrate Contacts and Layout
Week 4
Week 5
-
Notes on PLA Design,
-
- Text file containing "count.meg" PLA example,
-
Notes on IRSIM Test Vectors,
-
"A Clocking Discipline for Two-Phase Digital Systems,"
by D. Noice, R. Mathews, J. Newkirk,
- "A Formal Model of MOS
Clocking Discplines," by K. Karplus,
Week 6
Week 7
-
"Exclusion Constraints, a new application of Graph Algorithms to VLSI
Design," by K. Karplus,
Week 8
-
Notes on Crystal Timing Analysis
-
Use of MPLA to generate ROMS and Decoders
Week 9
-
Notes on Spice Analysis of Pseudo-nmos and Static Complementary CMOS Circuits
-
Notes on Spice Analysis of Dynamic Domino CMOS AND Gate Circuits
Week 10
-
HSPICE Simulation from Magic Layout
Week 11
-
Notes on Pspicetool_0_5 script for HSPICE preparation
-
Notes on 0.5 Micron MOSIS AMI Process and local files
-
Padframes for MOSIS DIP and PGA Packages for 0.5 micron
-
MOSIS/Tanner Notes on 0.5 micron pad cells: PadBiDir, PadGnd, PadVdd
-
MOSIS Scalable Rules - Look at SCN3ME with submicron option for 0.5 C5N
Process
Week 12
- "Section 2.2
Notes and Figures on Wafer Processing from "ASICS", by
M. Smith,
-
MOSIS Minimum Density and Antenna Rules - Look for AMI C5N Process
-
Notes on CIF File Creation and Well Error Correction
Week 13
-
Notes on Layout Density Calculators
Week 14
-
MOSIS notes on 1.5 micron Padframe
-
Full MOSIS/Tanner Notes on 0.5 micron pad cells
-
Guidelines on Final Class Presentation
-
Guidelines on Final Project Report Format
-
Notes on Final Layout and Project Submission to MOSIS
-
Final MOSIS Project Checklist
Week 15
Fall 2003 - Homework Assignments
Typically five homeworks during the first 10 weeks of the semester
covering these topics: Basic VLSI cell layout, Compound Gates, Static
Latch Design, Finite State Machine Design and PLA Implementation, PLA
Interfacing to Logic, System Timing Analysis, Other CMOS Logic
Families, Approximate RC Timing Analysis, Spice Circuit Analysis.
-
Homework #1 Due: 09/26/03 - Compound Gates, Static Latch,
Barrel Shifter.
-
Homework #2 Due: 10/10/03 - PLA Design, PLA Interfacing to Logic,
Substrate Contacts
-
Homework #3 Due: 10/24/03 - System Timing of Accumulator
and Pipelined ALUs, Timing Analysis with Crystal
-
Homework #4 Due: 11/05/03 - Other CMOS Logic Families -
Pseudo-NMOS and Domino Logic
-
Homework #5 Due: 11/20/03 Problem 1 -
Approximate RC Timing Analysis,
Problems 2,4,5 Due: 11/24/03 Spice Analysis, CIF Well Creation, Minimum Density
Rules, Two-Phase Timing Analysis
MOSIS Run Status
The fall 2003 projects will be fabricated using the AMI 0.5
micron CMOS process through MOSIS generously
supported by the Semiconductor
Industry Association.
Course Topics
The topics covered in this course include:
- Overview of combinational Logic and minimization
- Sequential logic and Finite State Machines
- Overview of semiconductor physics
- PMOS and NMOS transistors
- CMOS fabrication technology (crystal growth, wafers,
lithography, masks, doping, etc.)
- Layout, design rules, stick diagrams
- The latch-up effect, prevention, well contacts
- Common structures (gates, compound gates, latches, shifters,
PLA's)
- Clocking strategies, 2-phase non-overlapping clock, Karplus
methodology
- Design Process - hierarchical design (regularity, modularity,
locality)
- Design verification tools (simulators, netlist comparators, DRC
checkers, etc.)
- MOS equations, second-order effects.
- Biasing, AC and DC characteristics, load lines
- Circuit parameters, parameter extraction
- Timing, power, and size tradeoffs
- Other CMOS structures: dynamic CMOS, pseudo NMOS, BiCMOS
- Introduction to testing and testability
- Analog CMOS
Sections of Course Manual - Not Complete
CADENCE Tool Tutorial for Rice Installation
CAD Tool Man pages
- Section 1 - cif2ps,
cifplot,
crystal,
eqntott,
esim,
espresso,
ext2sim,
ext2spice,
extcheck,
fsleeper,
irsim,
magic,
magicusage,
meg,
mkcp,
mpla,
net2ir,
nutmeg,
pplot,
prepspice,
rsleeper,
sconvert,
sim2spice,
sleeper,
spcpp,
spice.
- Section 3 - irsim-analyzer,
mpack.
- Section 5 - cmap,
displays,
dlys,
dstyle,
espresso,
ext,
glyphs,
magic,
mfbcap,
mpanda,
mpla,
net,
netchange,
sim,
simfile.
User contributed notes
Previous Years
About the VLSI Design class in
Fall 2002, and
Fall 2001, and
Fall 2000, and
Fall 1999, and
Fall 1998, and
Fall 1997, and
Fall 1996, and
Fall 1995
Joe Cavallaro
Last modified: 26 August 2003